The present invention relates to a logic semiconductor integrated circuit (LSI) provided with a central processing unit (CPU) and a digital signal processing unit (DSP) and formed into a semiconductor integrated circuit and an art effectively applied to a data processor (e.g. single-chip microprocessor or single-chip microcomputer) for high-speed processing.
Japanese Patent Application No. 296778/1992 (corresponding to U.S. Pat. Ser. No. 08/145,157) is a document describing a single-chip microcomputer in which an arithmetic and logic unit and a multiplier are mounted on the same semiconductor chip.
According to the above invention, a logic LSI chip includes a central processing unit, a bus, a memory, and a multiplier and particularly has a command signal line for transferring a command for a multiplication instruction related to read data from the central processing unit to the multiplier while reading the data out of the memory. As a result, because the command of the multiplication instruction related to read data is transferred from the central processing unit to the multiplier while the central processing unit reads data out of the memory, it is possible to directly transfer data between the memory and the multiplier.